Consumers are demanding more realistic, visual information in the office and in the home. Their demands are driving the need to move video, 3-D graphics, and photo-realistic image data from camera to personal computers and printers through local access network, phone, and satellite systems to home set top boxes and digital video cam recorders. Low Voltage Differential Signaling (LVDS) provides a solution to this consumer demand in a variety of applications in the areas of personal computing, telecommunications, and consumer/commercial electronics. It is an inexpensive and extremely high performance solution for moving this high speed digital data both very short and very long distances: on a printed circuit board and across fiber or satellite networks. Its low swing, differential signaling technology allows single channel data transmission at hundreds of megabits per second (Mbps). In addition, its low swing and current mode driver outputs create low noise, meeting FCC/CISPR EMI requirements, and provide a very low power consumption across frequency.
There are LVDS standards under two standards organizations: a Scalable Coherent Interface standard (SCI-LVDS) and an American National Standards Institute Telecommunications Industry Association Electronic Industries Association standard (ANSI/TIA/EIA). In an interest of promoting a wider standard, these standards define no specific process technology, medium, or power voltages. This means that LVDS can be implemented in CMOS, GaAs or other applicable technologies, migrating from 5 volts to 3.3 volts to sub-3 volt power supplies, and transmitting over PCB or cable thereby serving a broad range of applications. Thus, a valuable characteristic of LVDS is that the LVDS drivers and receivers do not depend on a specific power supply, such as 5 volts. Therefore, LVDS has an easy migration path to lower supply voltages such as 3.3 volts or even 2.5 volts, while maintaining the same signaling levels and performance.
This same valuable characteristic of drivers and receivers independent of power supply specifications poses a disadvantage in that difficulty arises when there are several receivers of multiple voltages integrated within a LVDS application accessible to one bus. Such is the case as shown in FIG. 1 where a 3.3V LVDS receiver 16 and 5V LVDS receiver 22 use the same bus 24 within an LVDS application such as a telecommunication router 10. As discussed, the power supply of each receiver 16 and 22 may be any combination of either 2.5, 3.3, or 5 volts since LVDS technology standards require no specific power supply voltage. The router 10 receives two signals from the drivers 12 and 18 of two switches (not shown). Both LVDS drivers 12 and 18 are coupled to two respective LVDS buses 14 and 20. At the opposite end of each LVDS bus 14 and 20, an LVDS receiver is coupled, 16 and 22, to each respective bus 14 and 20. The first receiver 16 has a 3.3V power supply and the second receiver 22 has a 5V power supply. Each LVDS receiver 16 and 22 is coupled to a bus 24 within the router 10 and generates current to drive a load attached to the bus 24. For this particular example, the load is a microprocessor 26. In operation, when one receiver accesses the bus 24, the other goes into a high impedance mode disabling itself from the bus 24. Accordingly, when each receiver 16 and 22 uses the bus 24, its power supply charges the bus 24. Thus, when the 5V receiver 22 gains access to the bus 24, its output buffer (not shown) drives the bus 24 from ground to 5 volts. The first receiver 16 at 3.3V power supply must be able to survive exposure to 5 volts during the high impedance mode without conduction of leakage currents flowing into the internal circuitry of the receiver 16. In summary, the output buffer of every receiver on the bus must be able to survive exposure to a voltage at least equal to the highest supply voltage of any receiver on the bus in order to prevent the conduction of leakage currents from flowing from the bus to the receiver.
Designing the output buffer of a 3.3 V LVDS receiver 16 using thick oxide 5 volt transistors is an approach towards preventing damage from exposure of higher power supply voltages. LVDS high speed applications, such as 400 Mbps applications, use fabrication processes suitable for high-speed, mixed signal designs. Yet, the implementation of thick oxide transistors in fabrication processes suitable for high-speed digital data has a negative impact on the speed of the receiver. Thus, the implementation of thick oxide transistors is not an acceptable solution.
As illustrated in FIG. 2, Davis describes a three-state output buffer circuit having a protection circuit in U.S. Pat. No. 5,455,732, which is hereby incorporated by reference. Davis provides a built-in protection against power-rail corruption by bus-imposed voltages when the buffer is in its high-impedance state. In particular the circuit uses a pseudo-power rail which can be used to adjust the bias on the output transistor's bulk and so to prevent a leakage path from occurring between the output node and a power rail via the output transistor source/bulk junction. NMOS transistor QN80 is the output pull-down transistor, driven by pull-down-transistor driver transistor QN60. Transistor QN70 is the pull-down transistor disabler. The gate of transistor QP10 is coupled to the input. QN10 is coupled in series to QP10. QN50 is coupled in series to QN10. QP20, QN20, QN40, QP50 and QN70 are all coupled in series with one another in this respective order. The enabling signal EB feeds the gates of transistors QP50 and QN70; while the enabling signal E feeds the gate of transistor QP20, QP30, and QN50. The source of QP30 is coupled to the circuit LINK+. The function of LINK+ is to enable the high-potential power rail to energize PV.sub.CC, to be coupled to V.sub.CC, but only when the voltage of the power rail is higher than that of the pseudo-rail PV.sub.CC, the rail coupled to the node common to QP30 and LINK+. Pull-up transistor QP40, coupled to the drain of QP30, is coupled to the comparison circuit COMP. The output signal lead OUT taken from the node common to transistors QP40 and QN80 is coupled to the comparison circuit COMP.
This design, however, incorporates low turn-on threshold voltage transistors, QN10, QN20 and QN40, which increase the complexity of design and thus, cost. In addition, during the high impedance mode when the output buffer is disabled from the bus, the voltage applied to the gate of QP40 is V.sub.CC minus a threshold voltage of approximately 0.4 to 0.5 volts. Accordingly, a leakage current will exist across this transistor QP40 when the voltage on the output lead OUT is greater than V.sub.CC. Thus, this design does not eliminate leakage current completely. In addition, QP10 is required to be a thick oxide transistor which unfortunately has a negative impact on the speed of the receiver and, thus, is not an acceptable solution for high speed applications such as 400 Mbps applications using the fabrication processes suitable for high-speed, mixed signal designs.
FIG. 3 illustrates a third design approach for implementation of the output buffer in a LVDS receiver using a first and second Schottky diode, S1 and S2 to prevent current from conducting into the output buffer. In addition to diodes S1 and S2, the output buffer 100 includes a plurality of p-channel transistors QP100, QP102 and QP104, an n-channel transistor QN100 and a current source I.sub.1. Transistor QP100 has a source coupled to a first power supply rail V.sub.CC, a gate coupled to an input node IN, a drain coupled to a first diode S1 and a backgate. The first Schottky diode S1 is coupled between transistor QP100 and the current source I.sub.1. Transistor QP104 has a gate coupled to power supply rail V.sub.CC. Transistor QP102 has a gate coupled to the source of transistor QP104 and the common node to Schottky diode S1 and current source I.sub.1. The second Schottky diode S2 is coupled between the first power supply rail V.sub.CC and the backgates of transistors QP100, QP102 and QP104 for driving the output. The output node OUT and drains of transistors QP102 and QP104 are tied to the drain of transistor QN100. Transistor QN100 has a gate coupled to the input node IN and a backgate and source coupled to the second power supply rail GND.
In operation, when voltage applied to a bus coupled to the output node OUT is greater than the power supply reference voltage Vcc, p-channel transistor QP104 turns on. Accordingly, p-channel transistor QP102 turns off, preventing current from flowing into the first power supply rail V.sub.CC. To prevent the backgate parasitic diodes of transistors QP100, QP102, and QP104 from conducting current though to the first power supply rail V.sub.CC, a Schottky diode S2 is used to block this path from the output node OUT to the first power supply rail V.sub.CC. In addition, the Schottky diode S1 blocks the voltage from damaging transistor QP100 and the rest of the circuitry internal to the receiver. Diode S1 also prevents current from conducting into the power supply rail V.sub.CC. Unfortunately, many fabrication processes for LVDS do not include a Schottky diode design implementation; thus, this approach is not feasible. Fabrication processes that do include Schottky diode implementation typically suffer an increase in cost, gain in die area and increase in process complexity.
Lentini et al describes a three-state CMOS output buffer circuit having a protective circuit in U.S. Pat. No. 5,852,382, which is hereby incorporated by reference. FIG. 4 illustrates the output buffer 150 which couples the bulk electrode of the pull-up transistor to a line whose voltage is always the highest between the supply voltage of the integrated circuit and the voltage of the external bus. The buffer 150 includes an inverter 7, a NOR gate 5, a NAND gate 3, an auxiliary circuit 9, a pull-up transistor M15, and a pull-down transistor M16. The pull-up transistor M15 has a bulk electrode connected to a switchable bulk line 2. The auxiliary circuit 9 keeps the switchable bulk line 2 connected to the voltage supply V.sub.DD as long as the voltage of the output node O is not higher than the supply voltage V.sub.DD. The NAND gate 3 includes circuitry for transferring the voltage of the output node to the switchable bulk line when the voltage of the output node exceeds the supply voltage. This design, however, fosters significant damage to the integrated circuit when a voltage higher than 5 volts is applied to the external bus. In the high impedance mode, the enable/disable signal E is low. Since the enable signal is coupled to the gate of transistor M11, zero volts is applied to the gate. If, hypothetically, a voltage higher than 5 volts is applied to the external bus when the output buffer 150 is in the high impedance mode, this same voltage will be applied to the source of M11. Thus, transistor M11 will experience a gate to source voltage that is greater than 5 volts. Particularly in a process where the gate voltage cannot exceed 5 volts, M11 will be stressed and damaged. Even though this design eliminates leakage current, it does not protect the internal circuitry from exposure to a higher voltage and, thus, damage may result.
In conclusion, there are existing designs that use 3V transistors and circuit techniques to prevent damage to internal circuitry and to prevent conduction of leakage currents. These techniques, however, are either too slow for LVDS applications or use components not available in most LVDS fabrication processes because of the cost and complexity added to the process. Hence, a need exists for an output buffer design of an LVDS receiver that prevents damage of internal circuitry of the receiver when exposed to bus voltages higher than the output buffer's power supply voltage.